Analog and Mixed Signal Layout Intern

The Analog and Mixed Signal Layout team is seeking a highly motivated and innovative engineer who will be accountable for designing physical layout of custom analog and digital components. As an Analog and Mixed Signal R&D Engineering Intern, you will be working on a variety of advanced SERDES IP projects including the latest standards in 112G and 128G SERDES. This position offers an excellent opportunity to work with skilled local and global teams of analog, digital and mixed signal engineers to deliver high-end solutions for various customers in a fast-paced environment. In this position, you will have an opportunity to explore the latest cutting edge semiconductor technologies and learn from experts in this field. Positions are available in our Markham and Mississauga offices.

The Solutions Group provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.