Analog Design, Sr Manager

• Manage and mentor the activities of a team of senior engineers focused on high-speed SERDES IP development across multiple projects
• Define architecture specifications and circuit implementation requirements for next-generation SERDES PHY IPs
• Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight
• Identify and refine circuit architectures to achieve optimal power, area and performance targets.
• Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components
• Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes
• Continuously drive design methodology improvements and adoption of latest EDA tools/flows
• Hire, develop and retain top analog engineering talent through active mentorship

• MSc with 8+ years experience of IC design with a strong background in SerDes architectures
• 2+ years of people management experience leading high-performance analog design teams
• Familiarity with transistor level circuit design and CMOS design fundamentals
• Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation
• Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques
• Hands-on experience with analog/mixed-signal design flows, tools, modeling
• Understanding of FinFET transistor characteristics and design challenges at advanced nodes
• Strong project management skills with the ability to manage multiple priorities
• Excellent communication and people leadership abilities to motivate cross-functional teams
• Good communication and documentation skills

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