ASIC Digital Design, Manager

Synopsys

Nepean, ON

Number of positions available : 1
Salary To be discussed
Published on November 29th, 2024
Add to favorites
Starting date : 1 position to fill as soon as possible

View complete profile Apply Now

Description

Category Engineering Hire Type Employee Job ID 5494 Remote Eligible No Date Posted 22/09/2024

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.
DDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR PHY IP products. All current and next-generation technologies are being developed by the DDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.
We are looking for ASIC Digital Design Manager to join Synopsys DDR PHY IP team to lead innovation and development of the world-class market-leading DesignWare DDR PHY IP solution.

Job Description

Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs
You will manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams
You will lead the team to deliver the design and achieve the best timing, performance, and power goals

Required Skills

BS/MS in Electrical Engineering with at least 6 years of experience in complex technical development

2 years of experience in people management, developing employees
Experience with synthesizable Verilog and System Verilog design concepts and implementation
Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques
Exhibit excellent communication skills and be self-motivated
Understanding of DDR memory and DDRPHY architecture is a plus

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.