ASIC Digital Design, Sr Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned ASIC Digital Design Engineer with a passion for cutting-edge technology and innovation. You excel in designing and developing advanced silicon solutions and have a deep understanding of DDR PHY IP. With a strong background in synthesizable Verilog and System Verilog, you bring a wealth of experience in front-end design flows, including linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques. Your excellent communication skills and self-motivation drive you to collaborate effectively with cross-functional teams, contributing to the successful development and implementation of high-performance, high-bandwidth, low-latency, and low-power products. You are detail-oriented, proactive, and thrive in a dynamic, fast-paced environment, always eager to push the boundaries of what's possible in semiconductor design.

• Contribute to all phases of DDR PHY IP design, from specification to productization.
• Design and micro-architect DDR PHY IP, writing Verilog and SystemVerilog code and design specifications.
• Conduct simulation and analysis of designs, collaborating with Verification, Timing, DFT, and Power team members.
• Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues.
• Maintain and improve design automation flow and processes.
• Provide customer support for integrating DDR PHY IP into their SoCs.

• Drive the development of market-leading DDR PHY IP solutions.
• Enhance the performance, bandwidth, latency, and power efficiency of our products.
• Innovate and push the boundaries of DDR PHY IP development.
• Contribute to the success of Synopsys' semiconductor design and verification tools.
• Elevate the capabilities and performance of our customers' SoCs.
• Shape the future of semiconductor design through continuous technological advancement.

• BS or MS in Electrical Engineering with at least 5+ years or 3+ years' experience respectively in complex technical development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts, coding, and implementation.
• Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques.
• Excellent communication skills and self-motivation.
• Understanding of DDR memory and DDR PHY architecture is a plus.

• Detail-oriented and proactive.
• Collaborative and team-oriented.
• Innovative and forward-thinking.
• Adaptable and able to thrive in a dynamic environment.
• Passionate about technology and continuous improvement.

Join the Synopsys DDR PHY IP team, a global and diverse group of experts dedicated to developing world-class DDR PHY IP solutions. Our team is committed to pushing the boundaries of performance, efficiency, and innovation in semiconductor design. Collaborate with talented professionals who share your passion for technology and excellence and contribute to the development of the next generation of high-performance, high-bandwidth, low-latency, and low-power products.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.