Design Verification Engineer, Staff

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned professional with a passion for digital verification and a knack for problem-solving. You have a strong background in Electrical Engineering, with hands-on experience in Verilog, System Verilog, and scripting languages like Perl or Python. Your proficiency in the UVM verification environment sets you apart. You excel in debugging and can root-cause issues efficiently. Your excellent communication skills enable you to work effectively with architects and RTL designers, providing technical leadership from initial specification to tape out. Experience with DFI, DDR PHY, or memory subsystems is a plus, but your willingness to learn and adapt is what truly makes you a valuable team member.

• Developing test benches and verifying integrated IP subsystems for global customers
• Triage and resolve issues by working independently with architects and RTL designers
• Providing technical leadership in verification from initial specification to tape out
• Collaborating with cross-functional teams to ensure seamless integration
• Implementing and maintaining UVM verification environments
• Debugging and root causing issues to ensure high-quality deliverables

• Accelerate the development of high-performance silicon chips
• Ensure the reliability and efficiency of chip designs
• Reduce project timelines by eliminating months off schedules
• Contribute to innovations in self-driving cars, AI, cloud, 5G, and IoT
• Enhance the overall quality of our verification processes
• Drive technical excellence within the verification team

• BSEE in Electrical Engineering with 5+ years of industry experience or MSEE with 2 years
• Proficiency in Verilog and System Verilog
• Experience with Perl/Python scripting
• Strong skills in UVM verification environment
• Excellent debugging and problem-solving skills
• Experience in DFI, DDR PHY, or memory subsystems is a plus

• A collaborative team player with strong communication skills
• Detail-oriented with a focus on quality and accuracy
• Innovative thinker with a passion for technology
• Self-motivated and able to work independently
• Adaptable and willing to learn new technologies

You will be part of the DDR PHY IP team, a group of dedicated professionals focused on developing and verifying high-performance digital IP. The team collaborates closely with architects, designers, and other verification engineers to deliver top-notch solutions to our global customers. Together, we strive to push the boundaries of technology and innovation.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.