Digital Verification Intern
Synopsys
Ottawa, ON-
Number of positions available : 1
- Salary To be discussed
- Published on October 16th, 2024
-
Starting date : 1 position to fill as soon as possible
Description
This Internship will be a duration of 16 Months for undergraduate (bachelors) students. Duration can be flexible For Masters Students. You'll be seated in our Ottawa office. As part of our team, you will get experience in:
- A experienced team will provide training to ramp you up to the position.
- Learning mixed-signal verification technics
- Defining and tracking verification testplans
- Designing and writing constrained-random SystemVerilog testbenches using UVM (Universal Verification Methodology)
- Creating and examining Functional Coverage
- Writing SystemVerilog assertions
- Debugging RTL and gate-level simulation failures
- Code and functional coverage analysis
Skill Requirements
- Excellent knowledge of digital design theory, semiconductor lifecycle and related topics
- Good knowledge of UVM concepts
- Proficient in HDL language such as SystemVerilog and Verilog
- Scripting experience with Perl, Python, Bash, or Csh is an asset.
Education Requirements
- Enrolled in Computer Engineering, or Electrical Engineering with focus on digital design, semiconductor and related topics.
- Please include your transcripts along with your resume.
Requirements
undetermined
undetermined
undetermined
undetermined
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