Experienced ASIC Digital Design Engineer

Synopsys

Markham, ON

Number of positions available : 1
Salary To be discussed
Published on September 16th, 2024
Add to favorites
Starting date : 1 position to fill as soon as possible

View complete profile Apply Now

Description

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world’s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Experienced ASIC Digital Design Engineer

Key Qualifications

BSEE or MSEE in digital design and verification
Must be familiar with Verilog and VCS.
Good knowledge of back-end synthesis tools DC/PT is desirable.
Scripting experience in Shell, Perl, Python and TCL is a plus.
Good theoretical and practical knowledge of digital signal processing and data recovery circuits is desirable.
Good communication skills for interacting between different design groups and customer support teams are required
Must be self-motivated, proactive, and able to apply good design quality while meeting tight deadlines
Resolves issues in inventive ways and exercises sound judgment in selecting methods and techniques to obtain solutions.

Preferred Experience

RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog.
Strong experience of ASIC Digital Design, front end experience.
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
Enhancing and maintaining existing SERDES PHY IP.
Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams