Experienced Design Verification Engineer

Experienced Design Verification Engineer

Responsibilities

• Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
• Write test cases, checkers, and coverage that implement the verification test plan.
  

Job Requirements

• Bachelors or Masters with relevant digital verification experience in the industry
• Experience of verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA
• RTL verification using coverage driven verification techniques
• Scripting in any language. Programming experience or coursework in C, C++
• Proficient in HDL languages System Verilog, Verilog, or VHDL
• Good analytical, oral, and written communication skills
• Self-motivated, proactive team player
  

Unique opportunities presented with this position

• To grow and manage verification of product end-to-end.
• Cross-functional learning and interaction with professional teams across domains and geographies.
• Customer-facing role working in close collaboration with pre and post-sales team
• Develop systematic ways to address new problems, think outside of the box
• Have an impact on the new product architectures, quality and development strategies

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.