Sr. Staff Analog and Mixed Signal Design Engineer

• Circuit-level PLL design and PLL top-level modeling and simulation
• Design of analog circuits such as VCOs, charge pumps and voltage regulators
• Custom circuit design in deep-submicron and FINFET CMOS technologies
• Design of high-speed digital circuits such as dividers and clock distribution paths
• Schematic entry and spice simulation of custom circuits
• Provide mentoring and technical leadership to junior designers
• Coordinate and interface with layout and CAD teams

• 8+ years of experience within CMOS analog and mixed-signal circuit design with MSEE or PhD. Candidates with a Bachelor’s degree and additional experience will also be considered
• Detailed knowledge of PLL loop operation and design
• Experienced in design of SerDes blocks and/or PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers.
• Design experience in FINFET and gate all around CMOS technologies
• Hspice, Finesim, PrimeSim or similar spice-type simulators
• Schematic entry in Synopsys Custom Designer or similar tools
• Knowledge of digital timing in PrimeTime and/or Nanotime is an asset

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.