Staff Digital Design Engineer - 8248
Synopsys
Ottawa, ON-
Number of positions available : 1
- Salary To be discussed
- Published on December 24th, 2024
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Starting date : 1 position to fill as soon as possible
Description
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:We are seeking a highly motivated and innovative Senior Staff Digital Design Engineer with extensive knowledge of ASIC development flow. You possess over 8 years of experience in digital design or verification, demonstrating strong proficiency in developing RTL and verification plans. You excel in providing mentorship to both junior and senior engineers, fostering a collaborative environment. Your expertise includes advanced design methodologies, micro-architecture, Clock Domain Crossing (CDC), and Static Timing Analysis (STA). You are self-motivated, proactive, and committed to maintaining high design quality. Excellent communication skills enable you to interact effectively with different design groups. Your passion for technology drives you to stay ahead of industry trends, making you an invaluable asset to our team.
What You’ll Be Doing:- Developing and verifying RTL designs for next-generation digital IP controllers.
- Creating and utilizing advanced design methodologies for micro-architecture, CDC, and STA.
- Defining new architectures for protocols such as PCIe and UAL.
- Providing mentorship and guidance to junior and senior engineers.
- Collaborating with cross-functional teams to ensure seamless integration of designs.
- Driving innovations in semiconductor solutions for artificial intelligence (AI).
- Contributing to the development of cutting-edge semiconductor solutions.
- Enhancing the performance and efficiency of digital IP controllers.
- Shaping the future of AI through innovative design and verification techniques.
- Ensuring the highest quality and reliability of ASIC designs.
- Mentoring and developing the next generation of engineering talent.
- Driving Synopsys’ leadership in the semiconductor industry.
- Over 8 years of experience in digital design or verification.
- Proficiency in developing RTL and verification plans.
- Experience with advanced design methodologies, including micro-architecture, CDC, and STA.
- Strong knowledge of PCIe or Ethernet protocols.
- Excellent communication and collaboration skills.
- Self-motivated and proactive.
- Detail-oriented with a commitment to quality.
- Innovative and forward-thinking.
- Strong mentor and team player.
- Passionate about technology and continuous learning.
You will be working as part of a highly experienced design and verification team, targeting the next generation digital IP controllers. This team is dedicated to driving innovations in semiconductor solutions, particularly in the realms of artificial intelligence and advanced protocols such as PCIe and UAL. Collaboration and continuous improvement are at the core of our team's values, ensuring that we remain at the forefront of technological advancements.
Location:This position offers a hybrid working arrangement, allowing you to be based in either Markham or Nepean.
Rewards and Benefits:We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Requirements
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