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Staff R&D Design Engineer

Ottawa, ON
  • Number of positions available : 1

  • To be discussed
  • Starting date : 1 position to fill as soon as possible

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

The ideal candidate for this role is a seasoned professional with over 7 years of industry experience in analog or memory circuit design. You possess a strong foundation in transistor-level CMOS circuit design and are adept at using circuit simulation tools like XA/PrimeSim, HSIM, and HSPICE. Your experience spans across designing sense amplifiers, voltage regulators, charge pumps, and bandgap references. You bring hands-on experience with silicon debugging and have a basic understanding of Verilog simulation flow. As a team player, you exhibit excellent written and verbal communication skills, are detail-oriented, independent, self-motivated, and thrive in a multi-national, cross-functional team environment.

What You’ll Be Doing:

  • Contributing to all parts of advanced memory development flow, starting from design specifications.
  • Designing standard CMOS-based non-volatile memory circuits.
  • Designing and modifying charge pumps, voltage regulators, and sense amplifiers.
  • Collaborating closely with on-site and off-site design, layout, and CAD teams.
  • Conducting post-layout extraction and simulation.
  • Performing full chip level simulation and verification (both digital and analog).
  • Working with Product Engineers to perform silicon verification.

The Impact You Will Have:

  • Driving the development of next-generation NVM IP.
  • Enhancing the performance and reliability of memory designs.
  • Ensuring seamless integration of memory solutions across various process technologies.
  • Contributing to the innovation and advancement of Synopsys’ product offerings.
  • Collaborating with diverse teams to achieve project milestones and goals.
  • Helping maintain Synopsys’ leadership position in the semiconductor industry.

What You’ll Need:

  • 7+ years of industry experience as an analog circuit designer or memory circuit designer.
  • Strong fundamentals of transistor-level CMOS circuit design.
  • Proficiency with circuit simulation tools (XA/PrimeSim, HSIM, HSPICE, etc.).
  • Experience with industry-standard design and layout tools (Custom Compiler and ICV is a plus).
  • Hands-on experience with sense-amplifier, voltage regulator, charge pump, and bandgap reference design.
  • Experience with statistical design methodology (generating and analyzing Monte-Carlo results).
  • Experience with chip-level simulation.
  • Hands-on experience with silicon debugging.
  • Basic understanding of Verilog simulation flow is a plus.

Who You Are:

  • A team player with strong written and verbal communication skills.
  • Detail-oriented and organized.
  • Independent and self-motivated.
  • Able to work effectively with multi-national, cross-functional teams.
  • Passionate about innovation and technology.

The Team You’ll Be A Part Of:

You will be part of the Non-Volatile-Memory (NVM) team at Synopsys, collaborating with highly skilled professionals dedicated to developing cutting-edge memory solutions. Our team works on a wide range of process technologies and is committed to pushing the boundaries of innovation in memory design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.


Requirements

Level of education

undetermined

Work experience (years)

undetermined

Written languages

undetermined

Spoken languages

undetermined