ASIC Digital Design, Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned professional with a passion for ASIC digital design and verification. With 5-10 years of relevant experience, you possess a strong foundation in computer or electrical engineering, bolstered by hands-on experience in digital hardware verification. Your technical acumen includes proficiency in SystemVerilog, UVM, and scripting languages such as Python and Linux shell. You are adept at solving complex problems, debugging, and have excellent communication skills. Collaboration is second nature to you, and you thrive in a team environment. While not mandatory, your knowledge of PCIe or SERDES is a significant asset.

• Joining the Functional Verification team of PCIe7/Ethernet PHY.
• Contributing to developing verification strategies and verification plans.
• Creating state-of-the-art functional verification environments.
• Implementing, developing, and automating simulations and regressions.
• Generating verification reports and providing status updates during product development.
• Collaborating with peer design and verification engineers on debug and bug fixes.
• Staying up to date on state-of-the-art verification methodology and tools.
  
  

• Enhancing the robustness and reliability of our PCIe7/Ethernet PHY products.
• Driving the development of cutting-edge verification strategies that set industry standards.
• Streamlining simulation and regression processes to improve efficiency and accuracy.
• Ensuring timely and precise verification reports that guide product development decisions.
• Facilitating seamless collaboration within the design and verification teams for optimal outcomes.
• Contributing to the continuous improvement of verification methodologies and tools, keeping Synopsys at the forefront of technological innovation.
  
  

• 5-10 years of relevant experience in ASIC digital design and verification.
• Bachelor’s or Master’s degree in Computer/Electrical Engineering or Computer Science.
• Proficiency in SystemVerilog and UVM.
• Experience with Constrained-Random and Coverage-Directed verification.
• Strong scripting skills, including Python and Linux shell.

• Excellent problem-solving and debugging skills.
• Strong communication skills, both written and verbal.
• Exceptional interpersonal and collaboration skills within a team environment.
• Enthusiastic about staying updated on the latest verification methodologies and tools.
• Detail-oriented and committed to delivering high-quality work.
  
  

You will be part of the Functional Verification team, focusing on PCIe7/Ethernet PHY. This team is dedicated to developing and implementing state-of-the-art verification strategies and environments. Collaboration and innovation are at the core of our team, as we strive to maintain Synopsys' leadership in technology and innovation.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.