ASIC Digital Design, Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

As an ASIC Digital Design Engineer, you are a proactive and self-motivated professional with a keen eye for detail. You thrive in dynamic environments and excel at meeting tight deadlines without compromising on quality. Your communication skills are top-notch, enabling you to effectively interact with various design groups and customer support teams. You possess a robust theoretical and practical understanding of digital signal processing and SERDES, including data recovery circuits. Your expertise in Verilog RTL coding or modeling of analog blocks is complemented by your experience in defining synthesis design constraints, resolving STA issues, and handling gate-level simulation failures. You are adept at evaluating clock/reset domain crossing violations using CDC/RDC tools and have scripting experience in Shell, Perl, Python, and TCL.

• Designing and verifying ASIC RTL at both the chip and block level.
• Developing and coding in Verilog RTL and modeling analog blocks.
• Defining synthesis design constraints and resolving STA and gate-level simulation issues.
• Evaluating clock/reset domain crossing violations using CDC/RDC tools.
• Collaborating with various design groups and customer support teams to ensure seamless integration.
• Applying innovative solutions to complex design challenges while adhering to tight deadlines.

• Enhancing the performance and capabilities of silicon IPs (PCIe/Ethernet/USB PHYs) for SoCs.
• Reducing time-to-market for differentiated products with minimized risk.
• Driving innovations that contribute to the Era of Pervasive Intelligence.
• Ensuring high-quality design standards across all projects.
• Strengthening Synopsys’ leadership in chip design and IP integration.
• Fostering collaborative efforts within design groups and customer support teams.

• BSEE or MSEE with +5 years industry experience in mixed signal digital design and verification.
• Proficiency in Verilog RTL coding or modeling of analog blocks.
• Strong understanding of digital signal processing and SERDES, including data recovery circuits.
• Experience with synthesis design constraints and resolving STA issues.
• Familiarity with clock/reset domain crossing design constraints and CDC/RDC tools.
• Scripting skills in Shell, Perl, Python, and TCL are a plus.

• Excellent communicator with strong interpersonal skills.
• Self-motivated and proactive with a keen attention to detail.
• Innovative problem-solver with sound judgment.
• Able to work under pressure and meet tight deadlines.
• Collaborative team player with a customer-centric approach.

You will join a dedicated team that focuses on developing silicon IPs (PCIe/Ethernet/USB PHYs) to help customers integrate more capabilities into an SoC-faster. Our team is committed to meeting unique performance, power, and size requirements of target applications, ensuring differentiated products reach the market quickly with reduced risk.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.