Digital Design Verification Engineering Intern

• Program Length: 16 months
• Location: Mississauga, Canada
• Working Model: Hybrid working (50% working from home / 50% office)
• Full-Time/Part-Time: Full-Time
• Start Date: May 2025

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide-and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive-both at work and beyond.

• Defining and tracking Verification Testplans
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing SystemVerilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis

• Experience writing scripts in languages such as Perl, Unix shell, or Python
• Experience with any object-oriented programming language (C++, Java, Python, etc.)
• Familiar with Verilog or SystemVerilog
• Enrolled in Computer Engineering or Electrical Engineering program, or similar