Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

As a member of the NBIO, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. 

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

• Collaborate with design team to understand and define verification requirements for high-speed, low power digital circuit designs from definition to implementation.
• Own and be involved in all aspects of the functional verification from initial test planning, test creation and debug. to coverage and sign-off closure.
• Own and implement verification of high speed, low power digital designs at IP and System level using both coverage driven constraint random and directed testing techniques as well as formal verification.
• Own and implement test benches and components such as test and sequence libraries, monitors, models and BFMs by applying objected oriented programming verification techniques following UVM methodology.
• Work independently on various DV tasks and providing technical guidance to the DV team, or even lead a big DV task inside team or cross team.

PREFERRED EXPERIENCE:

• Extensive experience in digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow.
• Proficient with Verilog, System Verilog and UVM.
• Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)
• Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.
• Good in working in Linux and Windows environments.
• Familiarity with power aware simulation and firmware/hardware co-verification is a plus.
• Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus.
• Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus.
• Strong analytical and problem-solving skills with pronounced attention to detail.
• Scripting language experience: Perl, Ruby, Makefile, shell is a plus.
• Automating workflows in a distributed compute environment.
• Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Markham, ON

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.