ASIC Digital Design, Senior Engineer - 8477

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a highly motivated and innovative digital design engineer with a strong background in ASIC development, modeling, and digital signal processing. You bring a wealth of knowledge in high-speed serializer and data recovery circuits, making you an asset to any team. You have a solid theoretical and practical understanding of digital signal processing, and you are proficient in scripting languages like Shell, Perl, and Python. Your experience with block-level and system-level modeling using tools such as Matlab, Simulink, Verilog, or System Verilog sets you apart. You hold a BSEE or MSEE and have a minimum of 3+ years of digital design and verification experience in the industry. You excel in organization and communication, enabling you to interact effectively with different design groups and customers. Your expertise extends to high-speed digital & mixed-signal ASIC design, and you have a keen interest in analog design as well.

• Defining and developing ASIC RTL design and verification at both chip and block levels.
• Collaborating with a team of experienced digital and mixed-signal engineers to deliver high-end mixed-signal designs.
• Developing specifications and performing functional and performance tests on test-chips.
• Utilizing your scripting expertise to streamline design and verification processes.
• Modeling digital signal processing systems and components using Matlab, Simulink, Verilog, or System Verilog.
• Interfacing with different design groups and customers to ensure seamless project execution.

• Contributing to the development of next-generation flagship product architectures.
• Enhancing the quality and performance of high-speed SerDes PHY products.
• Driving innovation in digital and mixed-signal design methodologies.
• Improving customer engagement through high-quality deliverables.
• Advancing the state-of-the-art in ASIC digital design and verification.
• Collaborating across cross-functional domains to gain industry-leading knowledge.

• Relevant ASIC digital design experience in the industry.
• Strong scripting expertise in Shell, Perl, Python, etc.
• Good understanding of digital signal processing.
• Theoretical and/or practical understanding of high-speed SerDes PHY components.
• Experience with block-level and system-level modeling using Matlab, Simulink, Verilog, or System Verilog.

• A highly motivated and innovative engineer.
• An excellent communicator with strong organizational skills.
• A team player who thrives in a collaborative environment.
• A problem solver with a keen eye for detail.
• Adaptable and eager to learn new technologies and methodologies.

You will be part of a dynamic team of digital and mixed-signal engineers who are passionate about delivering high-end mixed-signal designs. Your colleagues are veterans in their fields, and you will have the opportunity to collaborate closely with them, gaining industry-leading knowledge and contributing to the development of next-generation products.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.