ASIC Physical Design, Sr Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world’s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

This position of “ASIC Physical Design Engr, Sr. Engineer” is for a Design Implementation Engineer who will primarily work on physical design activities of Mixed Signal DDR PHY IPs. The successful candidate will work on a variety of advanced DDR PHY developments including the latest standards in LP6, DDR5 and MRDIMM. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers.

Responsibilities:

Tasks will include but not be limited to, RTL synthesis and P&R flow using Synopsys tools, performing timing closure, constraints analysis, static and dynamic IR drop analysis, power estimation, electromigration checks and other physical verification tasks such as DRC/LVS/ERC/PERC,

Additional tasks will include scripting and coding for flow improvements, creation of views necessary for SOC integration of the hard macros and running all required QA checks before release of these views. The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.

Requirements:

• Requires a bachelor’s degree in electrical/electronic engineering (or equivalent) with 4+ years industry experience. Master’s degree is preferred
• Previous experience with Physical Design of IPs or SoCs with ability to handle broad responsibility for block-level physical design implementation and understanding of the full design cycle from RTL to GDSII, including chip level.
• Successful experience completing physical design in an advanced wafer technology
  (ex: FinFET, 16nm, 14nm, 12nm, 7nm, 5nm and below).
• Experience with Synopsys tools or other equivalent tools for Synthesis, P&R, Physical verification, STA, Formal, EM/IR, DFT

• Development of timing constraints and resolving STA problems to ensure on-time delivery of the PHY design blocks
• Experience with solving signal integrity and power integrity & DFT issues
• Scripting skill and experience using languages such as Tcl, Python, and/or Perl.
• Understanding of digital logic and RTL circuit representation.
• Strong engineering communication and collaboration skills.
• High motivation and determination to succeed.
• Solid understanding of the challenges inherent in analog/digital interfaces and the ability to find solutions to complex design issues.