Design Verification Engineering Internship

• Program Length: 16 months for Master's students
• Location: Markham, Ontario, Canada
• Working Model: Onsite
• Full-Time/Part-Time: Full-Time
• Start Date: May 2025

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide-and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive-both at work and beyond.

• Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Write test cases, checkers, and coverage that implement the verification test plan.
• Collaborate with design and architecture teams to understand the design specifications and derive verification requirements.
• Analyze and debug test failures to identify issues and drive them to resolution.
• Continuously improve verification methodologies to enhance efficiency and effectiveness.

• Master's degree with relevant digital verification experience.
• Proficiency in RTL verification using coverage-driven verification techniques.
• Scripting experience in any language, with programming experience or coursework in C, C++.
• Proficiency in HDL languages such as System Verilog, Verilog, or VHDL.

• Excellent analytical, oral, and written communication skills.
• Self-motivated and proactive team player.
• Detail-oriented with a strong problem-solving mindset.
• Adaptable and open to learning new tools and methodologies.
• Collaborative and able to work effectively in a team environment.

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.